At the technical forum, TSMC emphasized that the 3-nanometer process will be officially mass-produced in the second half of 2022. Competitor South Korea’s Samsung also said recently that the GAA-based 3-nanometer process technology will be officially taped out, which is the only two companies in the world. For semiconductor wafer foundries that can achieve a 5nm process or less, competition means a lot.

Foreign media reported that Samsung’s 3nm process tapeout progress is in cooperation with Synopsys to accelerate the provision of highly optimized reference methods for the production process of the GAA architecture. Because Samsung's 3nm process is different from TSMC or Intel's FinFET architecture, it is GAA architecture. Samsung needs new design and certification tools, so it uses Synopsys' Fusion Design Platform. The physical design kit (PDK) of the process technology was released in May 2019 and passed the process technology certification in 2020. This process is expected to enable Samsung's 3-nanometer GAA structure process technology to be used for high-performance computing (HPC), 5G, mobile and high-end artificial intelligence (AI) application chip production.

Sangyun Kim, vice president of Samsung's foundry design technology team, said that Samsung's foundry is the core of promoting the next stage of industrial innovation. Samsung will continue to develop technological processes to meet the growing demands of the professional and broad market. The latest and advanced 3nm GAA process technology of Samsung Electronics has benefited from the cooperation with Synopsys, and the Fusion Design Platform accelerates preparations to effectively achieve the promise of 3nm process technology, proving the importance and advantages of the key alliance.

Shankar Krishnamoorthy, general manager of the Digital Design Department of Synopsys, also said that the GAA transistor structure symbolizes a key turning point in the progress of process technology and is critical to maintaining the next wave of ultra-large-scale innovation. Synopsys and Samsung strategically cooperate to support the provision of first-class technologies and solutions to ensure the continuation of development trends and provide opportunities for the semiconductor industry.

GAA (Gate-all-around) architecture is a FinFET architecture surrounded by Gate. According to experts, GAA-based transistors provide better electrostatic characteristics than FinFETs and can meet certain gate width requirements. This is mainly manifested in the structure of the same size, the GAA's channel control ability is strengthened, and the size is more likely to be further reduced. Compared with the traditional FinFET channel with only 3 sides covered by the gate, if GAA takes the nanowire channel design as an example, the entire outer contour of the channel is completely covered by the gate, which means that the gate has better control over the channel.

The 3nm GAA process technology has two architectures, 3GAAE and 3GAAP. These are two designs with a nanosheet structure, with multiple horizontal strip lines in the fin. This kind of nanochip design has been studied by the research institute IMEC as a follow-up product of the FinFET architecture, and it has been developed in cooperation with IBM, Samsung and GF. Samsung pointed out that this technology is highly manufacturable, because about 90% of FinFET manufacturing technology and equipment are used, and only a small amount of modified photomask is enough. Another excellent gate controllability, 31% higher than Samsung’s original FinFET technology, and the width of the nanosheet channel can be directly changed graphically, making the design more flexible.

For TSMC, GAAFET (Gate-all-around FETs) is still the future development route. N3 technology node, especially N2 node may use GAA architecture. The pilot research model of advanced materials and transistor structures is currently being carried out. Another advanced CMOS research is currently underway. TSMC’s 3nm and 2nm CMOS nodes are progressing smoothly. TSMC has also strengthened its leading research and development work, focusing on nodes beyond 2 nanometers, as well as 3D transistors, new memories, low-R interconnects and other fields, which are expected to lay the production foundation for many technology platforms. TSMC is expanding the R&D capabilities of Fab12. Fab12 is currently researching and developing N3, N2 and even higher-end process nodes.