简体中文 English User Ctrl
User Ctrl
简体中文
简体中文 English
News Center

Industry says TSMC will commercialize CoWoS-L technology within 2 years

Feb 02 117
According to industry sources, TSMC has determined that its latest CoWoS process variant, CoWoS-L, is the only solution for 4 times the full reticle size in a 2.5D package. It is working with HPC chip customers to jointly address the challenges on the substrate side. It is expected to be released in 2023-2024. Commercial production began in 2010.

According to Digitimes, CoWoS-L is specially designed by TSMC for artificial intelligence training chips. According to its introduction, the process combines the advantages of TSMC CoWoS-S and information technology. Local Silicon Interconnect (LSI) chips and RDL layers for power and signal transmission provide the most flexible integration.

TSMC's CoWoS technology, a 2.5D wafer-level multi-chip packaging technology specially designed for HPC equipment applications, has been in production for nearly 10 years, the sources said. With CoWoS, TSMC has already won a lot of orders from high-performance computing processor suppliers such as AMD.

TSMC's traditional CoWoS technology with silicon interposer (CoWoS-S) has entered its fifth generation. The silicon interposer of CoWoS-S can reach more than 2 times the full mask size (1700mm2), integrating leading SoC chips with more than four HBM2/HBM2E stacks.

In a paper presented by TSMC for the 71st IEEE Electronic Components and Technology Conference (ECTC), the company introduced CoWoS-S5 technology using a novel two-pass lithography splicing method, 3 times the full reticle size (2500mm2) enables the silicon interposer to accommodate multiple logic chips of 1200mm2 and eight HBM stacks. In addition to the increased size of the silicon interposer, new features have been added to further enhance the electrical and thermal performance of CoWoS-S5 compared to the previous CoWoS-S combination.

TSMC also offers CoWoS-R, a CoWoS process variant that leverages its InFO technology to leverage the RDL layer for interconnection between chips, especially for HBM and SoC heterogeneous integration. The RDL layer is composed of polymer and trace amounts of copper and is relatively mechanically flexible.

Demand for HPC chips remains promising despite the recent growing uncertainty about demand for mass-market consumer electronics devices, the sources said. TSMC's enhanced CoWoS-S package and -R and -L process variants will be able to meet customers' different needs for their high-performance computing products. In the first quarter of 2022, orders for HPC chips surpassed that of smartphones, becoming TSMC's largest revenue contributor, and will drive its pure foundry revenue growth this year.