The Si5381/82/86 clocks are non-MEMS RF CMOS chips implementing the company’s ‘DSPLL’ technology (diagram below) to deliver a timing solution that combines 4G/LTE and Ethernet clocking in a single IC.

With DSPLL, of which this chip has the firm’s fourth generation, a low-jitter outer loop with a bandwidth below 10Hz surrounds a MHz bandwidth low phase-noise inner loop to get the best of both worlds, Silicon Labs spokesman James Wilson told Electronics Weekly. Loop filters are in the IC, reducing the chance of picking up board-level noise.

Silicon Labs DSPLL

The clocks eliminate the need for multiple clock devices and voltage-controlled crystal oscillators (VCXOs), and are aimed at small cells, distributed antenna systems (DAS), baseband units (BBU) and fronthaul/backhaul equipment.

As carriers transition to Ethernet-based eCPRI fronthaul networks to increase the capacity of fronthaul connections between base band units and remote radio heads, they are also deploying heterogeneous network (HetNet) equipment at the edge of the network where cost, power and size constraints present unique challenges for hardware designers.

Of the chips, each has at least one high-performance DSPLL supporting outputs up to 3GHz , plus one or more 700MHz general-purpose clocks. For example, the Si5386 has one low-phase-noise DSPLL for RF timing, plus five fractional clock synthesisers for Ethernet and baseband reference timing.

Outputs are connected to the synthesisers through a switching matrix.

Packages include a 9 x 9mm 64pin LGA.

Samples of the Si5381/82/86 wireless clocks are available now, and production quantities are planned for December.