TSMC (2330), a member of the Great Alliance, Synopsys announced yesterday (2) that it will assist TSMC in expanding its 5-nanometer process to accelerate product development. It will use TSMC's 5-nanometer process technology for high-performance computing system single-chip (SoC) and launch more IP portfolio , Scheduled to be launched at the end of this quarter, can accelerate the development of high-end cloud computing, AI accelerators, single chip development of network and storage applications.

Suk Lee, senior director of TSMC's design and construction management department, said that TSMC and Synopsys have long-term cooperation to provide customers of both sides with DesignWare IP based on the most advanced process technology, so that customers can achieve one-time completion in various markets such as efficient computing Silicon crystal design.

Through Synopsys' extensive DesignWare IP portfolio for TSMC's advanced process technology, it can help designers quickly integrate the necessary functions into the design, while benefiting from the most advanced wafer foundry solution, which is 5 nanometer process technology. The powerful power consumption and efficiency improvement.

Synopsys emphasizes that the combination of the company's DesignWare IP and TSMC's 5-nanometer process can help designers master the strict requirements of design in terms of performance, power consumption and density, while reducing integration risks, and allowing both Synopsys and TSMC customers to accelerate efficiency Can develop a single chip.

Synopsys' cooperation with TSMC also extends to three-dimensional (3D) IC process technology, including advanced packaging such as CoWoS, InFO and TSMC-SoIC. TSMC also attracts most chip makers to adopt these advanced packaging services by providing 5 Nano-processes produce high-performance computing (HPC), mobile, 5G and AI chips.