For Intel, the process is by no means a simple digital advancement, but a magical combination of multi-channel advancement. On August 13, Intel's 2020 Architecture Day set a new "reengineering" record again.

Intel Chief Architect Raja Koduri joined hands with a number of Intel academicians and architects to introduce in detail Intel’s progress in the six technological pillars of innovative manufacturing and packaging, architecture, memory and storage, interconnection, software, and security.

Based on these six technical pillars, Intel focused on the 10nm SuperFin technology related to the process, the "hybrid combination" technology related to packaging, the Willow Cove and Tiger Lake CPU architecture, hybrid architecture, Xe graphics architecture and data center architecture and related Software oneAPI Gold.

In terms of manufacturing process, the 10nm SuperFin technology is the most powerful single-node performance enhancement in the company's history, and the performance enhancement it brings is comparable to full-node conversion. The 10nm SuperFin technology realizes the combination of Intel enhanced FinFET transistors and Super MIM (Metal-Insulator-Metal) capacitors. Compared with industry standards, the capacitance has increased by 5 times in the same footprint, thereby reducing voltage drop and significantly improving product performance.

According to reports, the technology is realized by a new type of "high-K" (Hi-K) dielectric material, which can be stacked in ultra-thin layers with a thickness of only a few angstroms to form a repeating "superlattice" structure . This is a leading technology in the industry, ahead of the existing capabilities of other chip manufacturers.

In terms of packaging, test chips using "Hybrid bonding" technology have been taped out in the second quarter of 2020. It is understood that the traditional "thermocompression bonding" technology is used in most packaging technologies today, and hybrid bonding is an alternative to this technology. This new technology can accelerate the realization of bump pitches of 10 microns and below, providing higher interconnection density, bandwidth and lower power.

In terms of architecture, Intel introduced multiple architectures at once.

According to reports, Willow Cove is Intel's next-generation CPU microarchitecture. Willow Cove is based on the latest processor technology and 10nm SuperFin technology, and on the basis of the Sunny Cove architecture, it provides an improvement over inter-generational CPU performance, greatly improving frequency and power efficiency. It also introduces the redesigned cache architecture into the larger non-compliant 1.25MB MLC, and enhances security through Intel Control Flow Enforcement Technology.

Tiger Lake will provide intelligent performance and breakthrough progress in key computing vectors. Tiger Lake is the first SoC architecture to adopt the new Xe-LP graphics micro-architecture, which can optimize the CPU and AI accelerators, which will enable CPU performance to be improved beyond a generation, and achieve large-scale AI performance improvements and a huge leap in graphics performance , And a complete set of top IP in the entire SoC, such as the newly integrated Thunderbolt 4.

Not only that, the hybrid architecture Alder Lake is Intel's next-generation hybrid architecture client product, which can provide a better performance-to-power ratio.

When introducing the Xe graphics architecture, Intel introduced a number of products based on this architecture, including Xe-LP (low power), Xe-HP, Xe-HPG, Intel® Server GPU (SG1), DG1 and Intel® Graphics Command Center (IGCC).

Xe-LP is an optimized micro-architecture and software that can provide efficient performance for mobile platforms. This will enable new end-user features with instant game tuning (Instant Game Tuning), capture and streaming, and image sharpening. In terms of software optimization, Xe-LP will improve the driver through the new DX11 path and optimized compiler. Xe-HP is the industry's first multi-tiled, highly scalable, high-performance architecture. At the Architecture Day event, Intel demonstrated that Xe-HP transcodes 10 complete high-quality 4K video streams at a rate of 60 FPS on a single block. Another demonstration also showed the computational scalability of Xe-HP on multiple blocks. It is understood that Intel is now testing Xe-HP with key customers, and plans to enable developers to use Xe HP through Intel® DevCloud. Xe-HPG is a micro-architecture optimized for games, and a variant of Xe micro-architecture. It has good performance-to-power ratio, scalability, and accelerated ray tracing support.

Intel® Server GPU (SG1) is Intel’s first Xe-based discrete graphics card for data centers, which can increase performance to the data center level in a small size to achieve low-latency, high-density Android cloud games and video streaming . DG1 is Intel’s first discrete graphics card based on the Xe architecture and is now available on Intel® DevCloud for early access users. Intel® Graphics Command Center (IGCC) introduces new features, including real-time game adjustments and game sharpening.

When introducing the data center architecture, Intel introduced Ice Lake, Sapphire Rapids and the next-generation 224G-PAM4 TX transceiver. Ice Lake is the first 10nm-based Intel Xeon Scalable processor that will provide strong performance in terms of throughput and responsiveness across workloads. Sapphire Rapids is Intel's next-generation Xeon Scalable processor based on enhanced SuperFin technology. It will be the CPU used in the "Aurora Exascale" supercomputer system (Aurora Exascale) at Argonne National Laboratory. The world's first next-generation 224G-PAM4 TX transceiver is the product introduced this time.

In terms of software, Intel released its eighth version of oneAPI Beta in July, bringing new functions and improvements to distributed data analysis, including rendering performance, performance analysis, and video and thread library. The various technological innovations this time revealed the continuous progress of Intel's innovation strategy of "six technological pillars". Intel is making full use of its unique advantages to provide solutions that combine scalar, vector, matrix and spatial architectures, which are widely deployed in CPUs, GPUs, accelerators and FPGAs, and are unified by the open and industry-standard programming model oneAPI. This simplifies application development.

Product technical introduction:

10nm SuperFin technology

SuperFin technology can provide enhanced epitaxial source/drain, improved gate process and additional gate pitch, and achieve higher performance by:

Enhance the extension of the crystal structure on the source and drain to increase strain and reduce resistance to allow more current to pass through the channel;

Improve the gate technology to achieve higher channel mobility, so that charge carriers move faster;

Providing additional gate pitch options can provide higher drive current for chip functions that require the highest performance;

The use of a new thin-walled barrier reduces the via resistance by 30%, thereby improving interconnect performance.

Package

"Hybrid bonding" technology: An alternative to "thermocompression bonding" technology, it accelerates the realization of bump pitches of 10 microns and below, providing higher interconnection density, bandwidth and lower power.

Willow Cove CPU architecture

Willow Cove is based on the latest processor technology and 10nm SuperFin technology, and on the basis of the Sunny Cove architecture, it provides an improvement over inter-generational CPU performance, greatly improving frequency and power efficiency.

It also introduces the redesigned cache architecture into the larger non-compliant 1.25MB MLC, and enhances security through Intel Control Flow Enforcement Technology.

Tiger Lake CPU architecture

The Tiger Lake SoC architecture provides:

The new Willow Cove CPU core-based on the 10nm SuperFin technology advancement, significantly increase the frequency;

New Xe graphics architecture-with up to 96 execution units (EUs), the performance efficiency per watt is significantly improved;

Power Management-Autonomous Dynamic Voltage and Frequency Adjustment (DVFS) in a consistent structure to improve the efficiency of the fully integrated voltage regulator (FIVR);

Structure and memory-The bandwidth of the consistent structure is increased by 2 times, about 86GB/s memory bandwidth, verified LP4x-4267, DDR4-3200; LP5-5400 architecture function;

Gaussian network accelerator GNA 2.0 dedicated IP, used for low-power neural inference calculations, and reduce CPU processing. In the case of running audio noise suppression workload, the CPU utilization of GNA inference calculation is 20% lower than that of the CPU without GNA;

IO-Integrated TB4/USB4, integrated PCIe Gen 4 on the CPU, used for low-latency, high-bandwidth device access to memory;

Display-Up to 64GB/s simultaneous transmission bandwidth is used to support multiple high-resolution displays. Dedicated structure path to memory to maintain quality of service;

IPU6-up to 6 sensors, with 4K 30-frame video, 27MP pixel image; up to 4K90 frames and 42MP pixel image architecture function

Hybrid architecture

Alder Lake will combine Intel's upcoming two architectures-Golden Cove and Gracemont, and will be optimized to provide excellent performance-to-power ratio.

Xe graphics architecture

Xe-LP is Intel’s most efficient architecture for PC and mobile computing platforms, with a maximum configuration of up to 96 groups of EU units, and a new architecture design, including asynchronous computing, view instancing, and sampler feedback , An updated media engine with AV1 and an updated display engine, etc. This will enable new end-user features with instant game tuning (Instant Game Tuning), capture and streaming, and image sharpening. In terms of software optimization, Xe-LP will improve the driver through the new DX11 path and optimized compiler.

Xe-HP is the industry's first multi-tiled, highly scalable, high-performance architecture that provides data center-level and rack-level media performance, GPU scalability, and AI optimization. It covers the calculation of the dynamic range from one tile to two and four tiles, and its function is similar to a multi-core GPU.

Xe-HPG is a variant of Xe micro-architecture, which is a micro-architecture optimized for games. On the basis of the building blocks of Xe-LP, a new GDDR6-based memory subsystem is added to improve cost performance and will have accelerated light. Tracking support.

Intel® Server GPU (SG1) is Intel’s first Xe-based discrete graphics card for data centers. SG1 achieves the aggregation of 4 DG1s, which can improve the performance to the data center level in a small size to achieve low-latency, high-density Android cloud games and video streaming.

DG1 is Intel's first discrete graphics card for PCs based on the Xe-LP microarchitecture.

Intel® Graphics Command Center (IGCC) introduces new features, including real-time game adjustments and game sharpening. Instant game adjustment is a game-specific driver that can push repairs and optimizations to end users faster than before, and does not require downloading and installing complete drivers. It only requires users to choose to join once in each game; game sharpening uses perceptual adaptive sharpening, an adaptive sharpening algorithm based on computational shaders to improve image clarity in games. This feature is especially useful for games that use resolution scaling to balance performance and image quality, and is an optional feature in IGCC.

Data center architecture

Ice Lake is the first Intel Xeon Scalable processor based on 10nm. Ice Lake products will provide strong performance in terms of throughput and responsiveness across workloads. It will bring a series of technologies, including full memory encryption, PCIe Gen 4, 8 memory channels, etc., and an enhanced instruction set that can speed up cryptographic operations.

Sapphire Rapids is Intel's next-generation Xeon Scalable processor based on enhanced SuperFin technology. It will provide leading industry standard technologies, including DDR5, PCIe Gen 5, Compute Express Link 1.1, etc.

software

oneAPI Gold provides developers with solutions that guarantee product-level quality and performance in scalar, vector, matrix and spatial architecture. DG1 discrete GPU is currently available to some developers on Intel® DevCloud, which contains DG1 libraries and toolkits to enable them to start writing DG1 related software using oneAPI before they own the hardware.